Tesla is working on HW4.0 self-driving chip with semiconductor company TSMC with a timeline for mass production in Q4 2021

[TruckElectric]

Tesla is working on HW4.0 self-driving chip with semiconductor company TSMC with a timeline for mass production in Q4 2021, according to a new report coming out of China.

Back in 2016, Tesla started building a team of chip architects led by legendary chip designer Jim Keller to develop its own silicon.

The goal was to design a super powerful and efficient chip for self-driving.

Last year, Tesla finally unveiled the chip as part of its Hardware 3.0 (HW 3.0) self-driving computer.

They claim a factor of 21 improvement in frame per second processing versus the previous generation Tesla Autopilot hardware, which was powered by Nvidia hardware, while only barely increasing the power consumption.

When launching the new chip, CEO Elon Musk announced that Tesla is already working on the next-generation of the chip and they expect it to be 3 times better than the new chip and roughly 2 years from production.

Now a new report from China Times reveals more information about the chip and its timeline to production (translated from Chinese):

“According to industry news, Broadcom and Tesla are cooperating to develop ultra-large HPC chips for automotive use. They are produced using TSMC’s 7nm process and are the first to use TSMC’s SoW advanced packaging technology. Each 12-inch wafer can only be cut out. 25 chips. Production of the new chips will begin in the fourth quarter, with an initial production of about 2,000 wafers, and it is expected to enter full mass production after the fourth quarter of next year.”

Tesla’s HW 3,0 chip was produced by Samsung, but it looks like Tesla wants to move to a 7 nanometer procress and TSMC, a Taiwan semiconductor company, is arguably the leader in the space.

According to the report, the chip is going to be used for “advanced driving assistance systems” and “self-driving cars”, amongst other things, leading us to believe that this is Tesla’s HW 4.0 chip:

“It is understood that the HPC chip created by Broadcom for Tesla will become the core computing special application chip (ASIC) for Tesla electric vehicles in the future, which can be used to control and support advanced driving assistance systems, electric vehicle power transmission, and car entertainment. The four major application areas of automotive electronics such as systems and car body electronic components will further support the real-time computing required for self-driving cars. The HPC chip jointly developed by Broadcom and Tesla should be an important cooperation project from electric vehicles to self-driving cars.”

The timeline in the report suggests first batch production as soon as Q4 2020, but that’s likely for engineering validation.

Mass production wouldn’t happen until Q4 2021 – meaning that we aren’t likely to see those chips inside Tesla production vehicles until 2022.

Electrek’s Take
It makes a ton of sense for Tesla to move to a 7 nm process since the main advantage is the ability to operate at a much lower supply voltage (sub 500mV), which should result in lower power consumption.

Power consumption is always a concern with chips, but it is especially the case for chips that go into cars and especially electric cars, due to the concerns over range and efficiency

Of course, in an electric car, the power consumption of the powertrain is going to dwarf the power consumption of the on-board computer, but with self-driving capabilities, on-board computers are starting to be more demanding and they affect efficiency.

Tesla’s next-gen chip using a 7 nm process could address that issue while still leaving room to improve performance.

Source: Electrek


Benzinga's Take: Tesla looks to be fully integrated, whether it's the seats they produce, computer hardware or even providing the means to produce energy for your vehicle in the form of solar panels.

Apple AAPL 0.13% made a similar move last year when it ditched Intel INTC 0.66% in favor of its in-house designed chip.

Hardware 4.0 also seems a possibility as Tesla's next vehicle, the Cybertruck, is expected to launch around the same time that this new TSMC chip is reportedly planned for mass production.

Source: Benzinga

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[TruckElectric]

FEBRUARY 4, 2008 WEBLOG
Intel Microchip Packs Two Billion Transistors
by Lisa Zyga , Phys.org.

Intel has just announced the first microchip that contains more than two billion transistors - tiny switches that together perform the calculations in computers. The chip, known as Tukwila, marks a milestone in chip density technology. Source: Phys.org


AUGUST 19, 2020
Cerebras breaks own record with improved densities via TSMC's 7 nm nodes: 2.6 trillion transistors and 850,000 cores on a single chip

The updated Wafer Scale Engine allows Cerebras to double the transistor and core counts on the monolithic chips, although the size and power requirements should remain close to the original gen 1 chips since the technology now uses TSMC's 7 nm nodes instead of the older 16 nm. It remains to be seen if Cerebras is going to double the amount of on-chip SRAM and the fabric bandwidth.
Bogdan Solca, 08/19/2020

Remember the huge 8x9-inch chips integrating 1.2 trillion transistors and 400,000 cores announced by Cerebras Systems last year? Those are about to become obsolete, as the company has recently announced that it has updated the Wafer Scale Engine (WSE) technology to benefit from TSMC’s 7 nm production nodes instead of the older 16 nm FF nodes, which would lead to improved densities.
At this year’s Hot Chips event, Cerebras teased the updated WSE, revealing only that the improved chips can now integrate 2.6 trillion transistors and 850,000 cores. Since Cerebras is now using the improved 7 nm nodes from TSMC, we are assuming that the size of the chip will not increase too much from the current 46,225 square millimeters, if at all. This also depends on the amount of SRAM memory that will be added for each core cluster. The first gen WSE included 18 GB of on-chip SRAM with 9 PB/s bandwidth, so we are expecting that amount to be doubled with the new generation, at least in regards to the memory capacity.

When it comes to chip bandwidth, things are not that clear-cut anymore, since Cerebras did not mention anything regarding possible improvements to the communication fabric that stitches together all the smaller chips. First gen WSE was capable of 100 Pb/s total fabric bandwidth.
Power requirements will most likely be kept as close to the original 15 kW as possible, since the jump from 16 nm to 7 nm should reduce power requirements by around 100%.

More details on the improved Wafer Scale Engine should be unveiled in the coming months, and Cerebras reports that it is currently running the new monolithic chips in its labs.

Source: Notebookcheck

 

[MEDICALJMP]

Interesting updates. Thank you.

 

[Gibbed187]

TMSC is the largest chip manufacturer in the world. They make about 65% of the world's active components. They are about 4 years ahead of Intel on new tech as well. Most people don't know the name because they build for companies like Fairchild, IR, LTC.

 

[Iacemoe]

My guess is that the new chip will be around the same TDP as the current model. From what I've seen of teslas electronics is that they are very densely populated. If they had stated that the next gen chip was going to be designed for efficiency purposes rather than a 3x performance increase over the current design, then I could see a small die targeting lower TDP specs.

With that said, moving to a tried and true 7nm TSMC process node is a great move.

 

[Gibbed187]

What the 7nm design allows you to do is stack tech with a smaller footprint. My guess is they'll create a new ASIC and stack newer tech allowing the boards to become smaller. For those of you that do not understand what stacking is, you can take multiple technologies (MCU, memory, passive) and have it all in one package (BGA, LQFN). So instead of 3 separate circuits on a board, it's all in one chip.

 

[TruckElectric]

TSMC North America located at Stone Creek II 11921 N Mopac Expressway Austin, TX is hiring.

Jobs posted:

SRAM Design Engineer 24 days ago

Job Location: Austin, Texas Hiring Manager: Director, Austin Memory Design Program Responsibilities: • Hands on development of compiler memories, with a focus on characterization and flow development. • Daily collaboration with local team members as well as frequent correspondence w/ overseas teams on various topics. • Analyze data, compare against expectations, identify errors/outliers, and then present/document an organized summary/evaluation of the results. • May perform other duties as assigned including special projects and other administrative responsibilities.

Requirements: -A Bachelor’s degree in E.E. with minimum 3 years’ experience in compiler memory development. -The following work experience will be the most helpful: • Experience with latest technologies and the challenges they present • Scripting and flow design and maintenance • Timing and Power characterization of compiler memories • Race condition and margin characterization and analysis -Be able and willing to participate in occasional off-hours conference calls (usually evening calls) and possible overseas travel. -Attention to detail is absolutely critical. -Able to follow instructions, oral and written, carefully and completely. -Good oral and written communication skills -Ability to get along with others, compromise, and work well on a team. -Ability to think on your feet and find solutions to overcome and/or work-around problems to achieve goals. TSMC Technology Inc. is an Equal Opportunity Employer


Analog Design Engineer - Data Converters 24 days ago

Job Location: Austin, TX Hiring Manager: Technical Manager, Design and Technology Platform Join a highly innovative team of mixed-signal designers using next generation advanced process technologies. This is an exciting position in a challenging and dynamic environment with excellent opportunities in R&D. Responsibilities: • Design innovative and leading-edge transistor-level analog circuits with emphasis in high speed and high resolution Analog-to-Digital converters (ADCs) using TSMC’s process technologies. • Work with R&D teams to advance process development and to foster technology adoption by our industry partners and customers. • Follow all the standard procedures, considerations and rigors of product development from conception to test. • Produce schedules, system-level models, transistor-level implementations, and comprehensive simulation data and test plans. • Perform detailed design reviews and publish results at major industry conferences.

Requirements: • Master degree in Electrical Engineering. PhD preferred. • At least 5+ years of direct experience preferred in high-speed (>100MSPS) and high resolution ADCs, including but not limited to SAR ADC, Pipelined/SAR ADC, Hybrid ADCs, Inter-leaving of ADCs. Experience in over-sampled ADCs (Switched Capacitor and high BW Continuous Time) architectures is a plus • Good understanding of device noise, mismatch, linearity and layout parasitics. • Ability to drive floorplan and layout toward successful tape-out using best-practice layout techniques. • Strong working knowledge of various analog building blocks including amplifiers, current sources, bandgap references, comparators, transconductors, switched-cap circuits, etc. • Recent and extensive project-lead experience in the development of CMOS mixed signal circuitry from concept to production is a plus TSMC Technology Inc. is an Equal Opportunity Employer

Digital Designer 5 days ago

Job Location: Austin, TX Hiring Manager: Sr Manager, Power Management Design Program Responsibilities: Work with Analog and Digital team to define chip architecture RTL development and verification (RTL and Gate level) Static timing constraint generation and analysis/signoff Lab evaluation and silicon debug RTL design and verification flow development Design documentation

Minimum Requirements: Bachelor's in Electrical Engineer or related field of study, plus 5+ years of relevant experience Complete understanding of ASIC design flow from RTL to GDSII Familiarity with the Verilog language and simulators A good understanding of analog functionality and exposure to analog IC design methods Ability to solve problems using a systematic approach Preferred qualifications: Master's in Electrical Engineer or related field of study and 10+ years digital/mixed signal ASIC architecture/design experience RTL coding and synchronous/asynchronous digital skills Experience with SystemVerilog Knowledge of PLL, DLL, SerDes, DDR3, I2C and SPI Simulation tools like NCsim, code coverage and debug tools Synthesis, STA, Lint checkers, Clock domain crossing (CDC) checkers, Logic equivalence checking Scripting skills in Perl, Tcl, Python etc Demonstrated strong analytical and problem solving skills Strong verbal and written communication skills Ability to work in teams and collaborate effectively with people in different functions Strong time management skills that enable on-time project delivery Ability to work effectively in a fast-paced and rapidly changing environment Ability to take the initiative and drive for results TSMC Technology Inc




Source: TSMC NORTH AMERICA AUSTIN, TX

 

[TruckElectric]

TSMC’s state-of-the-art plant in the southern city of Tainan has also started producing 5-nanometer chips designed for the new Apple iPhones. They are scheduled for launch in the second half of 2020, while the company expects its 3-nanometer chips to be ready for mass production by 2022. Source: Taiwan News


The question is: How low can you go?

Just for comparison a DNA molecule is ~2.5 nanometers in width